INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
GD
PVCC
OUT_SW
VDC
REG 1
UVLO 0
CS
UVLO 1
SLEW
BOOST
CONTROLLER
COMP
WITH
OVP
OVP/OCP
SHUT_B
SYNC_IN
SYNC_OUT
DVDD
OSCILLATOR
OTP
VLOGIC
REG 2
V SENSE
UVLO 2
CH1
DIO1
SHL
DIO2
DATA+
DATA-
CLK+
CLK-
SHIFT
REGISTER
DIFFERENTIAL
INTERFACE
8 CHANNEL
CURRENT
DRIVER
CH2
CH3
CH4
CH5
CH6
CH7
CH8
DGND
AGND
SETUP
RESET-SCAN
SCAN
LS
SETUPD
CONTROL
LOGIC
REFERENCE
TEST
SYNC_PWM
CPLL
PWM
GENERATOR
GENERATOR
ISET
REFIO
GNDIO
PGND
Figure 2. 34848 Simplified Internal Block Diagram
34848
Analog Integrated Circuit Device Data
2
Freescale Semiconductor
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